FIG. 1 (Prior Art) is a simplified top-down diagram of a field programmable gate array 1 having a plurality of logic modules 2 oriented in rows and columns and a plurality of programming control shift registers 3-10. A programmable interconnect structure (not shown) of routing conductors and antifuses is disposed between the logic modules. To realize a user-specific circuit in the field programmable gate array, a user connects selected digital logic elements in selected logic modules together by programming the appropriate antifuses of the programmable interconnect structure.
FIG. 2 (Prior Art) is a simplified top-down diagram illustrating the programming of an antifuse 11 to connect horizontal routing conductor 12 and vertical routing conductor 13. A programming control driver (not shown) of programming control shift register 3 places a high voltage (VHH) at least one threshold above a programming voltage (VPP) onto vertically extending programming control conductor 14 to turn programming transistor 15 on. A programming control driver (not shown) of programming control shift register 10 places VHH onto horizontally extending programming control conductor 16 to turn programming transistor 17 on. Next, a programming driver (not shown) of programming control shift register 3 drives programming voltage VPP onto vertically extending programming conductor 18 and a programming driver (not shown) of programming control shift register 10 drives ground potential (GND) onto horizontally extending programming conductor 19. A programming current therefore flows as indicated by the arrows through antifuse 11 to program it.
It may be desired that the user-specific circuit programmed into a field programmable gate array not be readily decipherable by others once the antifuses of the interconnect structure are programmed. It is, however, possible to use the programming control shift registers 3-10 to determine which antifuses in the interconnect structure are programmed and which are not. For example, it is possible to determine whether anitfuse 11 is programmed by loading the programming control shift registers 3 and 10 as illustrated in FIG. 2 and then measuring the magnitude of a current flowing through the field programmable gate array (for example, into the VPP terminal of the field programmable gate array). If there is no current flow, then antifuse 11 is not programmed. If, on the other hand, there is current flow, then antifuse 11 is programmed. By successively testing each antifuse in this way, it may be possible to determine which antifuses are programmed and which antifuses are not programmed and therefore to decipher the user-specific circuit programmed into the field programmable gate array. A circuit is desired which will prevent such testing of antifuses.
It may, however, be desirable to be able to interrogate a programmed field programmable gate array and to determine whether or not certain other antifuses have been programmed. Two different types of field programmable gate array devices may, for example, be packaged in the same type of package having the same number of external terminals. If before the packages are marked, the two packaged field programmable gate arrays are intermixed, then it would be difficult to determine which type of field programmable gate array is in a particular package. It is therefore desirable to provide an antifuse on each field programmable gate array which can be read after it is programmed. If, for example, this antifuse is read as being in a programmed state, then it is determined that the field programmable gate array in the package is of a first type. If, on the other hand, the antifuse is read as not be in a programmed state, then it is determined that the field programmable gate array in the package is of a second type.
A field programmable gate array is therefore desired wherein some antifuses of the interconnect structure cannot be read after programming but wherein other antifuses can be read after programming.